• System Verification: Develop and maintain SoC verification testbench in SystemVerilog. Expericence with coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups.
• Programming and debugging C test cases to verify IP integration into the system, including reusing and translating it from RTL subsystem verification environment for FPGA verification.
• Familiarity in working on UNIX/LINUX environment and being able to use command line based applications and experience in working with scripting languages like Python, Tcl, Makefiles, bash etc.

• Excellent theoretical and practical experience of RTL Verification utilising SystemVerilog, including SVA.
• Proficiency in C programming plus, ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++)
• Skilled in simulation Tools: Verdi/VCS, QuestaSim and Cadence tools.
• Confident user of a UNIX environment and shell programming/scripting in e.g. Makefile, Python, Tcl, sh, bash.
• Comprehension and use of data formats such as YAML and JSON.
• Practical embedded software knowledge to test and debug designs.
• Experienced with the implementation of ASIC/SoC RTL in FPGA
• Real hands-on expertise in debugging sophisticated designs
• Solid understanding of AMBA bus standards
• A creative and structured approach to problem-solving

• Experience working with SV UVM test benches, using UVM Verification IPs (VIP) (Desirable/Optional)
• Working with version control and project management/bug tracking systems such as SVN/Git and Jira.
• Xilinx FPGA technology.
• Synopsys tool flows.
• Experience using Arm DS5 / DSTREAM debugger (Desirable/Optional)
• Excellent written and spoken English; can write coherent documentation

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