Low-Power ADC/PLL design engineer

Low-Power ADC/PLL

Your new company
Chinese companies listed on NASDAQ

Your new role
Low-Power ADC/PLL design engineer

What you'll need to succeed

The Alibaba T-head division is looking for experienced designers in mixed-signal integrated circuits for edge devices. These designs include analog circuits and systems containing data converters, timing circuits like Phase Lock Loops (PLLs), RC oscillators, custom digital macros, low drop out linear voltage regulators, precision references, comparators. The role is also expected to perform analog and mixed-signal modeling and verification tasks, both at IP level and chip level.

Minimum Qualifications
Master degree with 5+ years of professional experience in the transistor level design of analog or mixed-signal integrated circuits.
Have architecture, design and production expertise in high-speed data converter architectures and circuits; digitally-assisted ultra-low-power analog circuits.
Good knowledge of high precision techniques in presence of device mismatch.
Low-power high-throughput SAR-ADC or high-speed PLL design experience is a must.
Skills in HW IP design with Matlab/Simulink, Verilog-A modeling and Verilog/VHDL, analog and mixed-signal module and chip level modeling and verification; AMS design flows and chip assembly techniques.
Able to work with design, layout and product test engineers to produce test plans and design for testability details.
Hands-on experience in using spectrum analyzers, oscilloscopes, signal generators, etc. to validate analog designs.
Experience in design for ESD compliance and safety.

What you'll get in return
- Internal development and promotion plan;
- Technical leading brand with big platform;
- Equity incentive;

What you need to do now
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Talk to a consultant

Talk to Sudan Peng, the specialist consultant managing this position, located in London-City

4th Floor, 107 Cheapside

Telephone: 02034650158

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